Course catalog description: Advanced topics in deep submicron and nanotechnology VLSI design and fabrication. Logic and state machine design for high performance and low power. Tree adders and Booth multipliers. Memory design. Timing testing for crosstalk faults. Design economics. Emerging nanotechnology devices.
Credits and contact hours: 3 credits; 1 hour and 20-minute session twice a week, every week
Pre-Requisite courses: 14:332:479
Co-Requisite courses: None
- Deep Submicron CMOS Circuit Fabrication accounting for process corners
- Deep Submicron CMOS transistor theory, Strained Silicon Technology, Dual Damascene Process for Copper Wiring
- Resistance, Capacitance and Inductance Calculation, Deep Submicron Transistor Models
- Crosstalk and design margins
- VLSI economics, tools, design methodology, and design flows
- NP Dynamic and Zipper CMOS, Advanced Latches and Flip-Flops, pass transistor logic
- Design to Eliminate Clock Skew, Time Borrowing from Latches
- Dynamic logic and clocking
- Tree Adders, Carry Save Adders, Booth and Wallace Tree Multipliers and Dividers
- DRAM Design, CAM and ROM,Testing
- Wave Pipelining & case study, Synchronizers, Arbiters,
- Power Distribution &Phase-Locked Loop Clocking, latchup and reliability
- Design for Low Power, clocking, and analog VLSI design
- Silicon-on-Insulator Technology, Single-Electron Transistors, Carbon Nanotubes, Quantum Dots, Spintronics
Textbook: N. H. E. Weste and D. Harris, CMOS VLSI Design: ACircuits and Systems Perspective, Addison Wesley; M. Bushnell and V. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer(optional).
Other supplemental material: class notes.