14:332:331 Computer Architecture and Assembly Language (Spring 2005)
TF 11:30 AM -12:50 PM, SEC 117

Instructor: Yanyong Zhang (yyzhang@ece)
Office: Core518
Office Hours: 10:00-11:00AM Tu,F

Teaching Assistants
TA:
Yinglung Liang
Li Zhang
Office:
Core516
Core619
Number:
445-0606
445-3304
Email:
ylliang@ece.rutgers.edu
emmalily@ece.rutgers.edu
Hours:
Thursdays, 4-5 PM
Thursdays, 4-5 PM

Announcements:

Exam 2 is scheduled on March 31st, Thursday, 7:40-9:40, Hill 114.

The following office hours are made available to you in this week:

Yanyong Zhang (instructor): Tuesday 10-11am, Wed 5:30-7:30 pm (core 518)

Li Zhang (TA): Thu 2-5 PM (Core 619)

Yinglung Liang (TA): Thu 3-6 PM (core516)

Exam 2 scope:

VHDL will NOT be tested

Number representation; basic arithmetic operations; basic logic operations; multiplication operation (including Booths algorithm)

Basic ALU design

CPU performance; CPI

Single-cycle datapath and control

333 project 2 is posted online.

Our first midterm exam will take place on Thursday, Feb 17, 7:40 - 9:40 in EN-B120. The following office hours are made available to you in this week: Yanyong Zhang (instructor): Tuesday 10-11am, Wed 10-11am, Thu 5-6 pm (core 518) Li Zhang (TA): Wed 1-4 PM (Core 619) Yinglung Liang (TA): Wed 4-5pm, Thu 3-5 PM (core516)

Homework 2 is posted online.

Lab starts from the second week.