Prerequisites 14:332:231 : Digital Logic Design 14:332:252 : Programming Methodology I Corequisites 14:332:333 : Computer Architecture Lab Required Texts: Patterson, David A. and Hennessy, John L., Computer Organization & Design, Morgan Kaufmann Publishers, 1998. Yalamanchili, Sudhankar, VHDL Starter's Guide Prentice-Hall, 1998. Course Description This course is intended to cover the principles of Computer Architecture to bridge the gap between lower-level gate logic (14:332:331) and the upper-level executable programs (14:332:252). It includes the instruction sets, computer arithmetic, processor, memory hierarchy, and peripherals. Lecture-by-lecture Syllabus Lecture Topic Reading HW 1 Sep 2 Course introduction PH: 1.1-1.2 2 Sep 5 Basics of a computer system PH: 1.3, A.9-A.10 HW1 3 Sep 9 Intro. to assembly programming PH: 3.1-3.3 4 Sep 12 Machine instructions, PH: 3.4, 3.7 HW2 loads/stores 5 Sep 16 Control flow instructions PH: 3.5 6 Sep 19 Supporting procedures PH: 3.6, A.6 7 Sep 23 Machine addressing modes PH: 3.8 HW2(due) HW3 8 Sep 26 Assemblers, linker/loaders PH: 3.9, A.1-A.5 Midterm Tue Time: Location: #1 Sep 30 9 Sep 30 Introduction to VHDL Y: Chp1-5 HW4 10 Oct 3 Number repr. and PH: 4.1-4.3 basic arith. op. 11 Oct 7 Basic logic operations; PH: 4.4 HW5 multiplication instruction 12 Oct 10 ALU design PH: 4.5 13 Oct 14 Building a datapath PH: 5.1-5.2 14 Oct 17 Building a datapath (cont'd) 15 Oct 21 A simple single cycle PH: 5.3, C.1-C.2 implementation 16 Oct 24 A simple single cycle HW6 implementation (cont'd) 17 Oct 28 A multicycle implementation PH: 5.4 18 Oct 31 Defining control; PH: 5.4, C.3 hardwired control 19 Nov 4 Microprogramming PH: 5.5, C.4-C.6 20 Nov 7 Intro to pipelining PH: 6.1 Midterm Tue Time: Location: #2 Nov 11 21 Nov 11 A pipelined datapath PH: 6.2 22 Nov 14 A pipelined datapath (cont'd) PH: 6.2 23 Nov 18 Pipelined control PH: 6.3 24 Nov 21 Data hazards and branch hazards PH: 6.4-6.6 25 Nov 25 I/O, exceptions, and interrupts PH: 5.6, 8.5, HW7 A.7-A.8 26 Nov 28 Exception and interrupt(cont'd) 27 Dec 2 Bus design PH: 8.3-8.4 28 Dec 4 Memory hierarchy PH: 7.1, B.5 29 Dec 9 Basics of caches PH: 7.2 30 Dec 12 Basics of caches (cont'd) HW7(due) Final Time: Location: Grading Policy: 7 Homeworks + pop quizzes 25% Midterm Exam 1 21% Midterm Exam 2 23% Final Exam 26% Class Participation 5% Other Downloadable Format DOC PDF