14:332:331 Computer Architecture and Assembly Language (Fall 2002)
TF 8:10-9:30 AM, SEC 111
Instructor: Yanyong Zhang (yyzhang@ece)
Office: Core518
Office Hours: 10:00-11:00AM Tu,F
Teaching Assistants
| TA: |
Liquan Chen
|
Lian Jiang
|
Li Zhang
|
| Office: |
Core516 |
Core510 |
Core511 |
| Number: |
445-0606 |
445-0599 |
445-5256 |
| Email: |
liquan@eden |
lianjian@eden |
emmalily@eden |
| Hours: |
N/A |
N/A |
W: 4-5 PM |
Announcements:
Midterm exam II scope:
- 2's complement binary number representation
- multiply instruction, shift instructions
- calculate signal delay (given either VHDL code or logic design)
- ALU design (You need to know issues here extensively. For instance,
ALU control signals, delay calculation, overflow detection, zero detection, etc.)
- single-cycle impelementation for MIPS datapth and control
Midterms are scheduled.
- Exam #1: Tue, Oct 1, 6:10-7:10PM, Hill 114
- Exam #2: Tue, Nov1 12, 6:10-7:10PM, Hill 114
Please let me know (via email) ASAP for any conflict.
Office hours before the exam:
- 11/08, Friday, 10:00 - 11:00, Core518 (instructor)
- 11/11, Monday, 3:00 - 5:00 PM , Core511 (TA)
- 11/12, Tuesday, 8:30 - 11:00, Core518 (instructor)
Tuesday, at the class time,
I will be in the classroom on Tuesday. We will first look at couple of examples together, then I
will hold office hours there until 9:30.
Homework 5 solution is up on the web. You can download it for your use in homework 6. Note that
the file will look all right in UNIX environment.