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Note: All reading assignments are in Wakerly.

Lec- ture | Date | Content | Reading | Slides |
---|---|---|---|---|

1 | T: 09/03 | Introduction | Chapter 1 | lec-1.pdf |

2 | F: 09/06 | Number systems ; Complement Number Representation | Ch. 2 Sections 2.1–2.5 | lec-2.pdf |

3 | T: 09/10 | Addition, Subtraction, Multiplication, and Division | Ch. 2 Sections 2.6, 2.8, 2.9 | lec-3.pdf |

4 | F: 09/13 | Boolean Algebra, Theorems, Standard Representation of Logic Functions | Ch. 4 Section 4.1 | lec-4.pdf |

5 | T: 09/17 | Combinational Circuit Analysis | Ch. 4 Section 4.2 | lec-5.pdf |

6 | F: 09/20 | Combinational Circuit Synthesis I | Ch. 4 Section 4.3 | lec-6.pdf |

7 | T: 09/24 | Combinational Circuit Synthesis II | lec-7.pdf | |

8 | F: 09/27 | Timing Hazards | Ch. 4 Section 4.4 | lec-8.pdf |

9 | T: 10/01 | Logic Documentation ; Three-State Devices | Ch. 6 Sections 6.1–6.3, 6.6 | lec-9.pdf |

10 | F: 10/04 | Decoders | Ch. 6 Section 6.4 | lec-10.pdf |

11 | T: 10/08 | Encoders | Ch. 6 Section 6.5 | lec-11.pdf |

F: 10/11 | -- | |||

12 | T: 10/15 | Multiplexers, Exclusive OR Gates, and Parity Circuits | Ch. 6 Sections 6.7, 6.8 | lec-12.pdf |

F: 10/18 | FIRST MIDTERM EXAM
includes Lectures #1 – #11
(in the classroom SEC-111, during the class period 12 – 1:20 p.m.) |
|||

13 | T: 10/22 | Comparators | Ch. 6 Section 6.9 | lec-13.pdf |

14 | F: 10/25 | Adders, Subtracters, and ALUs | Ch. 6 Section 6.10 | lec-14.pdf |

15 | T: 10/29 | Sequential Circuits: Latches | Ch. 7 Sections 7.1–7.2.3, Ch. 8 Section 8.2.3 |
lec-15.pdf |

16 | F: 11/01 | D Latch ; Flip-Flops | Ch. 7 Sections 7.2.4–7.2.7 Sections 7.2.10, 7.2.11 |
lec-16.pdf |

17 | T: 11/05 | Clocked Synchronous State-Machine Analysis | Ch. 7 Section 7.3 | lec-17.pdf |

18 | F: 11/08 | State Machine Design and Synthesis | Ch. 7 Section 7.4 | lec-18.pdf |

19 | T: 11/12 | Designing State Machines Using State Diagrams | Ch. 7 Sections 7.5–7.7 | lec-19.pdf |

20 | F: 11/15 | Sequential Logic Design Practices ; Counters | Ch. 8 Sections 8.1, 8.2, 8.4 | lec-20.pdf |

21 | T: 11/19 | Shift Registers | Ch. 8 Section 8.5 | |

F: 11/22 | SECOND MIDTERM EXAM includes Lectures #12 – #19 | |||

W: 11/27 | -- | |||

Changes in Designation of Class Days: Tue Nov 26 ← Thursday Classes; Wed Nov 27 ← Friday Classes
Thanksgiving Recess:
Thurs Nov 28—Sun Dec 1
| ||||

22 | T: 12/03 | Introduction to Verilog | Ch. 5 Sections 5.4.1–5.4.6 | lec-22.pdf |

23 | F: 12/06 | Verilog Structural and Behavioral Design | Ch. 5 Sections 5.4.7–5.4.10 | lec-23.pdf |

24 | T: 12/10 | Verilog Time Dimension and Test Benches | Ch. 5 Sections 5.4.11–5.4.15 | lec-24.pdf |

Regular Classes End: Wed Dec 11
| ||||

Th: 12/19 | FINAL EXAM:
Dec 19, 2013: 12:00 PM - 3:00 PM in room Hill-114
(Hill Center Bldg) |

Wednesday: 8:40 – 10:00 a.m. in **SEC-117**
and 5:00 – 6:20 p.m. in **Wright Lab Auditorium**

Date | Time | Content | TA |
---|---|---|---|

09/18 | 8:40 – 10 a.m. | Solve problems related to the material
covered in the first 5 lectures; answer questions related to homework #1 |
Mehrnaz Tavan |

5 – 6:20 p.m. | |||

10/02 | 8:40 – 10 a.m. | Solve problems based on the
material covered in lectures 6,7,8 (and perhaps 9): finding the minimal sum-of-products, minimal product-of-sums expression of a given logic function, identifying static timing hazards associated with the circuit realization of a minimal sum-of-products logic expression, finding the minimal sum-of-products expression when there are don’t-care values in the truth table of a logic function. |
Talal Ahmed |

5 – 6:20 p.m. | |||

10/16 | 8:40 – 10 a.m. | Timing hazards, decoders (especially 74LS139 and 74LS138),
and encoders (priority encoder 74LS148). Basic knowledge will be reviewed and exercise problems involving encoders and decoders solved. |
Xiangyi Gao |

5 – 6:20 p.m. | |||

10/30 | 8:40 – 10 a.m. | Solve problems related to the material
covered in Lectures 12–15; answer questions related to homework #4 |
Zahra Shakeri |

5 – 6:20 p.m. | |||

11/20 | 8:40 – 10 a.m. | Solve problems related to lectures 16–19; answer question questions related to homework #5 | Mehrnaz Tavan |

5 – 6:20 p.m. | |||

12/04 | 8:40 – 10 a.m. | Solve problems involving the use of synchronous
binary counters, shift registers, and ring counters (Lectures 20–21). |
Talal Ahmed |

5 – 6:20 p.m. | |||

12/11 | 8:40 – 10 a.m. | General review for the final exam. Concepts covered include: • Boolean algebra with an example • Comparator 74LS85 with problem solving • Decoder and encoder: 74LS139, 74LS138, 74LS148 - brief review • Multiplexer 74LS151 with an example • Adder and subtracter: Carry Look ahead, half adder, full adder, and ripple adder - brief review • Binary Counter, Shift Register, and Ring counter: counter design with Flip Flops - concept review • State machine: general design process and sequence detector examples |
Xiangyi Gao |

5 – 6:20 p.m. |

Page Created:Sep 4, 2013Last Modified:Wed Dec 11 13:30:53 EST 2013Maintained by:Ivan Marsic