Solutions #3:  NMOS

Question #1: NMOS gate

a.     NOR gate

b.     VGSS = 3V, VDSS=???

VGSL = VDSL = VDD – VDSS =VGSL = VDSL = VDD – VDSS =  5-VDSS

IDSL(SAT) = IDSS(OHMIC)

0.4x10-3/2*(4-VDSS)2 = 0.8x10-3(2VDSS - VDSS2/2)

Vo = VDSS = 1.33V

c.     VGSS* = 3V, VDSS* = ?

VGSL = 5V = VDSS* K*DSS* K*S 2*KS

IDSL(SAT) = IDSS*(OHMIC)

0.4x10-3/2*(4-VDSS)2 = 1.6x10-3(2VDSS* - (VDSS*)2/2)

Vo = VDSS* = 0.8V

d.     VOL = VT = 1V

Question #2: NMOS Inverter

a.     VOH = VDD –VT = 4V

b.     VGSS = 4V, VDSS = ? VGSL = VDSL = 5 - VDSS

0.2x10-3/2*(4-VDSS)2 = 1x10-3*(3VDSS – VDSS2/2)

VOL = VDSS = 0.45V

c.     VIL = VT = 1V

d.     VDSS = VIL = 1V, VGSS = ?, VGSL = 5 – 1 = 4V

0.2x10-3*4 = 1x10-3*[(VGSS –1) – 12/2]

VTH = VGSS = 1.9V

Question #3:

a.     V2 = 0.5V therefore VDSS = 0.5V.

VGSL = VGL – VSL = 5V – 0.5V = 4.5VSL = 5V – 0.5V = 4.5V

So VDSL = VGSL – VT = 4.5V – 1V = 3.5V

IDSL = KL/2(VGSL – VT)2 = 0.125*(3.5)2 = 1.53mA

V across R is therefore VDD – VDSL - VDSS = 5V – 3.5V – 0.5V = 1V

IR = 1.53mA

Therefore R = 1V/1.53mA = 654W

b.     IDSS = Ks[(VGSS – VT)*VDSS – ½ VDSS2] = 1.53mA (from Part A)

VGSS = 4V and VDSS = 0.5V

Ks = 1.53mA/(3*0.5 – ½ (0.5)2) = 1.53mA/1.375V2 = 1.11mA/V2

c.     With all 3 Qs ON, Ks' = 3KS (since the effective channel is 3 times as wide.)  Therefore, V'DSS = VGSS – VT – [(VGSS – VT)2 – 2*IDSS/KS')1/2

VGSS = 4V, VT = 1V, IDSS = 1.53mA and Ks' = 3*(1.11mA/V2)

VDSS' = 4V – 1V – [(3V)2 – 2*1.53mA/3.33(mA/V2)]1/2 = 0.157V

Operating point for QL:

VGSL' = VDD – VDSS' = 5V – 0.157V = 4.843V

VDSL' = VDD – VDSS' – IDS*R = 5V – 0.157V – 1.53mA*654W = 3.842 V

VDSL' = VGSL' – VT = 4.843V – 1V = 3.843V

Since VDSL' = VGSL'10.0pt;font-family:"Calisto MT"'>Since VDSL' = VGSL' – VT we can assume the QL is saturated.

Question #4:

VOH = VDD – VT = 5V – 1V = 4V

Since IDSL = IDSL' (where the ' indicates variable # of inputs.)

KL/2 (VGSL – VT)2 = n*KS [(VGSS – VT)*VDSS – ½ VDSS2]

VGSL = VDD –VDSS, VGSS = 4V, VT = 1V

KL = 2mA/V2, KS = 4mA/V2

Solve the equations for varying n with VDS = VOL:

KL/2 (VGSL – VT)2 = n*KS [(VGSS – VT)*VDSS – ½ VDSS2]

2/2 (5 - VDSS – 1)2 = n*4 [(4 – 1)*VDSS – ½ VDSS2]

16 - 8VDSS + VDSS2 = 12nVDSS – 2nVDSS2

(2n+1)VDSS2 – (8+12n)VDSS + 16 = 0

 N VDSS 11 0.930V 2 0.547V 3 0.388V

Question #5:

a.     In the composite transistor, KS' = KS/3, since the channel is effectively 3 times as long when all the switch transistors are conducing.  We an proceed using the same strategy from the previous problem

KL/2 (VGSL – VT)2 = (KS/n)[(VGSS – VT)*VDSS – ½ VDSS2]

VGSL = VDD –VDSS, VOH = VDD –VT = 5V – 1V = 4V = VGSS

1(5 – VDSS – 1)2 = 4[(4 – 1)VDSS – ½ VDSS2]

3VDSS2 – 20VDSS + 16 = 0

VOL = 0.929V

b.     IDS = KS * [(VGSS – VT)VDSS – ½ VDSS2]

IDS = 1(5 – 0.929 – 1) = 9.43mA

(KS/2)*VDSS2 – KS(VGSS – VT)VDSS + IDS = 0

For Q1, VGSS = 4V

6VDSS12 – 12(4-1)VDSS1 + 9.43 = 0

VDSS1 = 0.275V

For Q2, VGSS = 4V – VDSS1 = 3.725V

6VDSS22 – 12(3.725-1)VDSS2 + 9.43 = 0

VDSS2 = 0.306V

For Q3, VGSS = 4V – VDSS1 – VDSS2 = 3.419V

DSS2 = 3.419V

6VDSS32 – 12(3.491-1)VDSS3 + 9.43 = 0

VDSS3 = 0.350V

VDSS1 = 0.275V

VDSS2 = 0.306V

VDSS3 = 0.350V

# Question #6: NMOS NOR gate

a.     VOH = VDD – VT = 5V – 1V = 4V

b.     KS' = KSA + KSB + KSC = 3sub>SA + KSB + KSC = 3mA/V2

KS[(VGSS – VT)VDSS – ½ VDSS2] = ½ KL(VGLS – VT)2

VGSS = 3V, VT = 1V, VGSL = VDD - VDSS

3[(2)VDSS – ½ VDSS2] = 0.1(4 – VDSS)2

60VDSS – 15VDSS2 = (4 – VDSS)2

4VDSS2 – 17VDSS – 16 = 0

VDSS = 0.25V

c.     IDSS.= 3[2*.25 – ½ *.252] = 1.4mA

Question #7: NMOS gate

a.     VOH = VDD – VT = 4V

b.     VOL = VDSS

Note: In series, K' = K/#. In parallel, K' = K*#

(0.2/2)*[VGSL – VT]2 = (2/2)*[(VGSS – VT)VDSS – ½ VDSS2]DSS2]

VGSL = VDD – VDSS, VGSS = VDD – VT = 4V

0.1[4 – VDSS]2 = [3VDSS – ½ VDSS2]

6VDSS2 – 38VDSS + 16 = 0

VDSS = VOL = 0.454V

c.     For Q1: IDS = K[(VGS – VT)VDS – ½ VDST)VDS – ½ VDS2]

IDS = 2/2[(4 –1 )*0.454 – ½ *.4542] = 1.26mA

d.     For Q1 : 1.26 = 2[3VDS – ½ VDS2]

VDS2 – 6VDS + 1.26 = 0

VDS = 0.217V

e.     IDS = (K/2)*[VGS – VT]2 = 0.1*(3 – 1)2 = 0.4mA

Where VGSL(av) = 5 – (0.8*4 + 0.2*4)/2 = 3V

I = Q = CV = CDV/DT and DT = CDV/I

Where I = IDSS* - IDSL

IDSS = Ks/2(VGSS – VT)2 = ½ (4-1)2 = 4.5mA

Io = 4.5mA - .4mA = 4.1mA

DT = CDV/I = 100*2.4/4.1mA = 58.5ns

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