14:332:482 -- Deep Submicron VLSI Design

Course Catalog Description: 

14:332:482 -- Deep Submicron VLSI Design (3)
Advanced topics in deep submicron and nanotechnology VLSI design and fabrication. Logic and state machine design for high performance and low power. Tree adders and Booth multipliers. Memory design. Timing testing for crosstalk faults. Design economics. Emerging nanotechnology devices.

Pre-Requisite Courses: 

14:332:479

Pre-Requisite by Topic: 

1. Introductory VLSI Design
2. CMOS technology, dynamic clocked logic, layout design rules
3. Analog MOSFET timing analysis
4. Computer-aided design software tools and elementary circuit testing
5. Cell library construction

Textbook & Materials: 

N. H. E. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 3rd Ed., Addison Wesley, 2005

M. Bushnell and V. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000 (optional).

Overall Educational Objective: 

To introduce students to deep-submicron and nanotechnology aspects in CMOS VLSI Design

Course Learning Outcomes: 

A student who successfully fulfills the course requirements will have demonstrated:
1. How to design VLSI chip layouts to account for process corners and fabrication process variations.
2. How to design chip layouts for the latest, deep submicron processes that include extremely short-channel effects, extreme transistor leakage, chemical mechanical polishing, and antenna rules.
3. How to characterize digital circuits for crosstalk noise in the layouts.
4. How to analyze the economics of producing a VLSI chip.
5. How to design with deep-submicron dynamic footed and unfooted logic.
6. How to analyze clock skew and adjust circuit sequencing to handle it and how to borrow time from latches.
7. How to design advanced ALUs with tree adders, Booth-encoded multipliers, Wallace trees, and Dadda trees.
8. How to design DRAM, content-addressable memory, ROMs, and PLAs.
9. How to use wave pipelining in chip design.
10. How to design synchronizers and arbiters.
11. How to design a clock tree or spine with a phase-locked loop.
12. How to design chips for low power consumption.
13. How to design for silicon-on-insulator technology.
14. An understanding of the various types of emerging, quantum nanotechnology devices.

How Course Outcomes are Assessed: 

  • Homeworks (7): 40%
  • Midterm Exam: 30%
  • Final Exam: 30%


N = none S = Supportive H = highly related

Outcome

Level

Proficiency assessed by

(a) an ability to apply knowledge of Mathematics, science, and engineering

H

HW Problems, Exams

(b) an ability to design and conduct experiments and interpret data

H

Design Problems in HW and Exams

(c) an ability to design a system, component or process to meet desired needs within realistic constraints such as economic, environmental, social, political, ethical, health and safety, manufacturability, and sustainability

N

(d) an ability to function as part of a multi-disciplinary team

N

(e) an ability to identify, formulate, and solve ECE problems

H

HW Problems, Exams

(f) an understanding of professional and ethical responsibility

N

(g) an ability to communicate in written and oral form

S

HW Problems

(h) the broad education necessary to understand the impact of electrical and computer engineering solutions in a global, economic, environmental, and societal context

N

(i) a recognition of the need for, and an ability to engage in life-long learning

H

Homework, discussions during lectures

(j) a knowledge of contemporary issues

N

(k) an ability to use the techniques, skills, and modern engineering tools necessary for electrical and computer engineering practice

H

HW Problems, Exams

Basic disciplines in Electrical Engineering

H

HW Problems, Exams

Depth in Electrical Engineering

H

HW Problems, Exams

Basic disciplines in Computer Engineering

H

Layout problems and simulations in homework

Depth in Computer Engineering

H

Hardware design in homework

Laboratory equipment and software tools

H

HW Problems

Variety of instruction formats

S

Lecture, office hour discussions

Topics Covered week by week: 

Week 1: Deep Submicron CMOS Circuit Fabrication accounting for process corners
Week 2: Deep Submicron CMOS transistor theory, Strained Silicon Technology, Dual Damascene Process
for Copper Wiring
Week 3: Resistance, Capacitance and Inductance Calculation, Deep Submicron Transistor Models
Week 4: Crosstalk and design margins
Week 5: VLSI economics, tools, design methodology, and design flows
Week 6: NP Dynamic and Zipper CMOS, Advanced Latches and Flip-Flops, pass transistor logic
Week 7: Exam 1 and Design to Eliminate Clock Skew, Time Borrowing from Latches
Week 8: Dynamic logic and clocking
Week 9: Tree Adders , Carry Save Adders, Booth and Wallace Tree Multipliers and Dividers
Week 10: DRAM Design, CAM and ROM, Testing
Week 11: Wave Pipelining & case study, Synchronizers, Arbiters,
Week 12: Power Distribution & Phase-Locked Loop Clocking, latchup and reliability
Week 13: Design for Low Power, clocking, and analog VLSI design
Week 14: Silicon-on-Insulator Technology, Single-Electron Transistors, Carbon Nanotubes, Quantum Dots, Spintronics
Week 15: Review and Final Examination

Computer Usage: 

Moderate

Design Experiences: 

Minor

Contribution to the Professional Component: 

(a) College-level Mathematics and Basic Sciences: 0.0 credit hours
(b) Engineering Topics (Science and/or Design): 3.0 credit hours
(c) General Education: 0.0 credit hours
Total credits: 3

Prepared by: 
M. L. Bushnell
Date: 
May, 2011