14:332:437 -- Digital Systems Design

Course Catalog Description: 

14:332:437 -- Digital Systems Design (3)
Hardware description, simulation, and synthesis using the Verilog language. Design methodologies for combinational and sequential logic circuits and systems. Characteristics of microprocessors, fault-tolerant computer design, computer arithmetic, and advanced state machine theory. Digital machine organization for testing and fault-tolerance.

Pre-Requisite Courses: 

14:332:231, 252, 331

Pre-Requisite by Topic: 

1. Digital Logic Design
2. Flip-flop and State Machine Design
3. Programming Methodology
4. Computer Architecture

Textbook & Materials: 

P. Lala, Self-Checking and Fault-Tolerant Digital Design, Morgan Kaufmann Publishers, 2001.

D. Thomas and P. Moorby, The Verilog Hardware Description Language, 5th Ed, Springer, 2002.

M. Bushnell and V. Agarwal, Essentials of Electronic Testing for Digital
Memory & Mixed-Signal VLSI Circuits, Springer, 2000 (optional).

Overall Educational Objective: 

To prepare students for the design of practical digital hardware systems using Verilog

Course Learning Outcomes: 

A student who successfully fulfills the course requirements will have demonstrated:
1. An ability to describe, design, simulate, and synthesize computer hardware using the Verilog hardware description language.
2. An ability to rapidly design combinational and sequential logic that works.
3. An ability to rapidly design complex state machines (present in all practical computers) that work.
4. An ability to synthesize logic and state machines using an Automatic Logic Synthesis program.
5. An ability to implement state machines using Field-Programmable Gate Arrays.
6. An ability to design high-speed computer arithmetic circuits.
7. An ability to design a computer to be fault-tolerant.
8. An ability to design a computer memory using error-correcting codes.
9. An ability to design a computer so that it can test itself with built-in circuitry.

How Course Outcomes are Assessed: 

  • Homeworks (10): 12.5%
  • Practicum Exams (4): 12.5%
  • Two Mid-Term Exams: 45%
  • Final Exam: 30%


N = none S = Supportive H = highly related

Outcome

Level

Proficiency assessed by

(a) an ability to apply knowledge of Mathematics, science, and engineering

H

HW Problems, Exams

(b) an ability to design and conduct experiments and interpret data

S

Design Problems in HW and Exams

(c) an ability to design a system, component or process to meet desired needs within realistic constraints such as economic, environmental, social, political, ethical, health and safety, manufacturability, and sustainability

N

(d) an ability to function as part of a multi-disciplinary team

N

(e) an ability to identify, formulate, and solve ECE problems

H

HW Problems, Exams

(f) an understanding of professional and ethical responsibility

N

(g) an ability to communicate in written and oral form

S

HW Problems -- Written

(h) the broad education necessary to understand the impact of electrical and computer engineering solutions in a global, economic, environmental, and societal context

N

(i) a recognition of the need for, and an ability to engage in life-long learning

S

Home-work, discussions during lectures

(j) a knowledge of contemporary issues

N

(k) an ability to use the techniques, skills, and modern engineering tools necessary for electrical and computer engineering practice

H

HW Problems, Exams

Basic disciplines in Electrical Engineering

S

HW Problems, Exams

Depth in Electrical Engineering

S

HW Problems, Exams

Basic disciplines in Computer Engineering

H

HW Problems, Practicums, Exams

Depth in Computer Engineering

S

HW Problems, Practicums

Laboratory equipment and software tools

H

HW Problems, Practicums

Variety of instruction formats

S

Lecture, office hour discussions

Topics Covered week by week: 

Week 1: Fault Tolerance Fundamentals and Triple Modular Redundancy
Week 2: Advanced Combinational Logic Design
Week 3: Verilog Language - Standard Combinational Logic
Week 4: Verilog Language - Concurrency and Sequential Logic
Week 5: Verilog Language - Tri-State Logic, Examples
Week 6: State Machines – Timing Analysis, False Paths, Counters
Week 7: State Machines – Synthesis to Handle Timing Delays, Asynchronous Inputs
Week 8: Exam I, State Machine Synchronizers
Week 9: Fault Tolerance -- Time and Information Redundancy
Week 10: Fault Tolerance -- Parity, Arithmetic, Cyclic and Hamming Codes
Week 11: Computer Arithmetic, Wallace Tree Multipliers and Dividers
Week 12: Testing, Fault Modeling and Test Generation , Hourly Exam II
Week 13: Built-In Self-Testing, Design for Testability
Week 14: Packaging and Rapid Prototyping – Microprocessor Design
Week 15: Final Examination

Computer Usage: 

Students use the Synopsys Design_Analyzer tool to synthesize hardware from Verilog hardware descriptions, and the Synopsys vcs behavioral/logic simulator to simulate the Verilog descriptions.

Laboratory Experiences: 

There are 10 Homework assignments that require students to use the circuit design software in the laboratory.

Design Experiences: 

The 10 Homework assignments are all hardware design experiences.

Independent Learning Experiences : 

The 10 Homework assignments.

Contribution to the Professional Component: 

(a) College-level Mathematics and Basic Sciences: 0.0 credit hours
(b) Engineering Topics (Science and/or Design): 3.0 credit hours
(c) General Education: 0.0 credit hours
Total credits: 3

Prepared by: 
M. Bushnell
Date: 
May, 2011